General purpose input/output (GPIO) enables an integrated circuit designer to provide generic pins that may be customized for particular applications. For example, a GPIO pin is programmable to be either an output or an input pin depending upon a user's needs. A GPIO host or peripheral will typically control groups of pins which can vary based on the interface requirement. Because of the programmability of GPIO pins, they are often included in microprocessor and microcontroller applications. For example, an applications processor in a mobile device may use a number of GPIO pins to conduct handshake signaling such as inter-processor communication (IPC) with a modem processor.
With regard to such handshake signaling, a sideband signal is deemed as “symmetric” if it must be both transmitted and received by a processor. If there are n symmetric sideband signals that need to be exchanged, each processor requires n*2 GPIOs (one GPIO to transmit a given signal and one GPIO to receive that signal). For example, a symmetric IPC interface between a modem processor and an application processor may comprise five signals, which translates to 10 GPIO pins being necessary for the resulting IPC signaling. The need for so many GPIO pins for IPC communication increases manufacturing cost. Moreover, devoting too many GPIOs for IPC limits the GPIO availability for other system-level peripheral interfaces. The problem cannot be solved by moving the IPC communication onto the main data bus between the processors in that certain corner conditions are then violated.
In addition, a number of digital signaling protocols have been developed to support communication between integrated circuits in a system such as a mobile device. These signaling protocols are deemed herein as “digital” in that the transmitting circuit either drives its transmit pin high to a power supply voltage level or grounds the pin to transmit a bit. Examples of such digital signaling protocols include general purpose I/O (GPIO) and universal asynchronous receiver transmitter (UART). For example, a UART transmitter drives a digital signal over a transmit pin that is received on a receive pin at a UART receiver. The UART receiver samples the received signal using an oversampling clock to determine whether the received signal was binary high or low.
To reduce power consumption in these digital signaling protocols, various lossless data compression techniques have been utilized such as run length encoding (RLE). But run length encoding does not guarantee a fixed and predictable throughput enhancement as the degree of compression depends upon the randomness of the data. If the data transmission is completely random, run length encoding offers no benefit. Other more complex schemes offer improved throughput but are not compatible with digital signaling. For example, the use of a quadrature phase shift key (QPSK) scheme has twice the throughput of conventional digital signaling but requires the use of two independent sinusoidal sub-carriers. In contrast, a digital signal protocol is much simpler as the transmitter needs to merely drive its transmit pin to a power supply voltage and/or to ground during a symbol transmission. Similarly, a digital signaling receiver needs to merely determine whether a voltage high or low signal is being received at each sampling of an oversampling clock.
Accordingly, there is a need in the art for a GPIO architecture that can accommodate numerous input/output signals without requiring an excessive number of pins and that uses an improved digital signaling protocol with increased throughput and reduced power consumption.